Acies is continuously searching for young and brilliant engineers (MSc, PhD) for its R&D team. Other positions are open, from time to time.
Since Acies is based in Brescia province, students from Brescia University (UNIBS) and technical schools (IIS/ITIS Castelli, IIS Pascal Manerbio) are invited tu submit their candidatures.
Depending on work areas, at least one of the following is an essential requirement:
- In-depth knowledge of C and C++ languages, Java would be a plus; SQL too
- Verilog for FPGA development
- High precision analog electronics
- Power electronics (DC/DC and AC/DC converters, motor drivers)
- Industrial networking (Profinet, Ethernet/IP, EtherCAT, CANopen)
If you are interested, you can submit your application to our email address, sending all the following documents:
- presentation letter
- your CV
- MSc and/or PhD certificate
- list of university exams with dates and marks
- authorization to store and process electronically your personal data ('Autorizzo il trattamento dei miei dati personali ai sensi del Decreto Legislativo 30 giugno 2003, n. 196 "Codice in materia di protezione dei dati personali”.')